1. Field of the Invention
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to field effect transistors, such as P-channel transistors, comprising an embedded strain-inducing semiconductor alloy and a high-k metal gate electrode formed in an early manufacturing stage.
2. Description of the Related Art
The fabrication of complex integrated circuits requires the provision of a large number of transistor elements, which represent the dominant circuit element in complex integrated circuits. For example, several hundred millions of transistors may be provided in presently available complex integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuits, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. In CMOS circuits, complementary transistors, i.e., P-channel transistors and N-channel transistors, are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies, such as CPUs, storage chips and the like. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor or generally a field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions and an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For example, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity in combination with desired channel controllability.
Upon continuously reducing the channel length of field effect transistors, generally, an increased degree of capacitive coupling is required in order to maintain controllability of the channel region, which may typically require an adaptation of a thickness and/or material composition of the gate dielectric material. For example, for a gate length of approximately 80 nm, a gate dielectric material based on silicon dioxide with a thickness of less than 2 nm may be required in high speed transistor elements, which may, however, result in increased leakage currents caused by hot carrier injection and direct tunneling of charge carriers through the extremely thin gate dielectric material. Since a further reduction in thickness of silicon dioxide-based gate dielectric materials may become increasingly incompatible with thermal power requirements of sophisticated integrated circuits, other alternatives have been developed in increasing the charge carrier mobility in the channel region, thereby also enhancing overall performance of field effect transistors. One promising approach in this respect is the generation of a certain type of strain in the channel region, since the charge carrier mobility in silicon strongly depends on the strain conditions of the crystalline material. For example, for a standard crystallographic configuration of the silicon-based channel region, a compressive strain component in a P-channel transistor may result in a superior mobility of holes, thereby increasing switching speed and drive current of P-channel transistors. The desired compressive strain component may be obtained according to well-established approaches by incorporating a strain-inducing semiconductor material, for instance in the form of a silicon/germanium mixture or alloy, in the drain and source areas within the active region of the P-channel transistor. For example, after forming the gate electrode structure, corresponding cavities may be formed laterally adjacent to the gate electrode structure in the active region and may be refilled with the silicon/germanium alloy which, when grown on the silicon material, may have an internal strained state, which in turn may induce a corresponding compressive strain component in the adjacent channel region. Consequently, a plurality of process strategies have been developed in the past in order to incorporate a highly strained silicon/germanium material in the drain and source areas of P-channel transistors, wherein the efficiency of the strain mechanism critically depends on the material composition of the silicon/germanium mixture, i.e., on the germanium concentration, and the amount of the mixture and its offset from the channel region. These aspects, in turn, are determined by the depth and shape of the cavities formed in the active region.
During the continuous reduction of the critical dimensions of transistors, also an appropriate adaptation of the material composition of the gate dielectric material has been proposed such that, for a physically appropriate thickness of a gate dielectric material, i.e., for reducing the gate leakage currents, nevertheless, a desired high capacitive coupling may be achieved. Thus, material systems have been proposed which have a significantly higher dielectric constant compared to the conventionally used silicon dioxide-based materials, silicon oxynitride materials and the like. For example, dielectric materials including hafnium, zirconium, aluminum and the like may have a significantly higher dielectric constant and are, therefore, referred to as high-k dielectric materials, which are to be understood as materials having a dielectric constant of 10.0 or higher when measured in accordance with typical measurement techniques. As is well known, the electronic characteristics of the transistor elements also strongly depend on the work function of the gate electrode material which influences the band structure of the semiconductor material in the channel region separated from the gate electrode material by the gate dielectric material. In well-established polysilicon/silicon dioxide-based gate electrode structures, the corresponding threshold voltage, strongly influenced by the gate dielectric material and the adjacent electrode material, is adjusted by appropriately doping the polysilicon material in order to adjust the work function of the polysilicon material at the interface between the gate dielectric material and the electrode material. Similarly, in gate electrode structures, including a high-k gate dielectric material, the work function has to be appropriately adjusted for N-channel transistors and P-channel transistors, respectively, which may require appropriately selected work function adjusting metal species, such as lanthanum for N-channel transistors and and aluminum for P-channel transistors. For this reason, corresponding metal-containing conductive materials may be positioned close to the high-k gate dielectric material in order to form an appropriately designed interface that results in the target work function of the gate electrode structure. In many conventional approaches, the work function adjustment may be performed at a very late manufacturing stage, i.e., after any high temperature processes, which may require the replacement of a placeholder material of the gate electrode structures, such as polysilicon, and the incorporation of appropriate work function adjusting species in combination with an electrode metal, such as aluminum and the like. In this case, however, very complex patterning and deposition process sequences may be required on the basis of gate electrode structures having critical dimensions of 50 nm and significantly less, which may result in severe variations of the resulting transistor characteristics.
Therefore, other process strategies have been proposed in which the work function adjusting materials may be applied in an early manufacturing stage, i.e., upon forming the gate electrode structures, wherein the corresponding metal species may be thermally stabilized and encapsulated in order to obtain the desired work function and thus threshold voltage of the transistors without being unduly influenced by the further processing. For this purpose, it turns out that, for P-channel transistors, an appropriate adaptation of the valence band energy of the channel semiconductor material may be required in order to appropriately set the work function of the P-channel transistors. For this reason, frequently, a so-called threshold adjusting semiconductor material, for instance in the form of a silicon/germanium mixture, may be formed on the active regions of the P-channel transistors prior to forming the gate electrode structures, thereby obtaining the desired offset in the band gap of the channel semiconductor material.
The threshold adjusting semiconductor alloy, such as the silicon/germanium material, is typically provided within the active region of P-channel transistors on the basis of a selective epitaxial growth process, wherein, frequently, the active region may be recessed prior to actually depositing the semiconductor alloy. Consequently, upon forming sophisticated semiconductor devices comprising strain-inducing mechanisms, threshold adjusting semiconductor alloys and the like, complex etch processes may have to be performed in order to form recesses or cavities for accommodating the epitaxially grown semiconductor alloy, wherein the overall transistor characteristics may critically depend on the uniformity of the involved etch processes, as will be described in more detail with reference to FIGS. 1a-1d. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in which a strain-inducing mechanism is to be implemented in at least one type of transistor on the basis of a strain-inducing embedded semiconductor material. In the manufacturing stage shown in FIG. 1a, the semiconductor device 100 comprises a substrate 101 above which is formed a semiconductor layer 103, such as a silicon layer. The semiconductor layer 103 and the substrate 101 may form a bulk configuration when the semiconductor layer 103 is a part of a crystalline material of the substrate 101. In other cases, as indicated by the dashed lines, a buried insulating layer 102, such as a silicon dioxide layer and the like, is frequently formed below the semiconductor layer 103, thereby providing an SOI (silicon-in-insulator) configuration. It should be appreciated that bulk architectures and SOI architectures are both used in many fields of semiconductor products in order to implement very sophisticated circuit elements on the basis of critical dimensions of 50 nm and less.
The semiconductor layer 103 comprises an isolation structure 103C, for instance in the form of a shallow trench isolation and the like, thereby laterally delineating a plurality of semiconductor regions or active regions, wherein, for convenience, a single active region 103A is illustrated in FIG. 1a. The active region 103A represents a portion of the layer 103 in which an appropriate basic doping is provided in order to form the PN junctions of at least one transistor 120, which in the present example represents a P-channel transistor. In the manufacturing stage shown, a gate electrode structure 110 is formed on the active region 103A and comprises a gate dielectric material 113 which separates an electrode material 112 from a channel region 123, which represents a portion of the active region 103A. The gate electrode structure 110 may further comprise a dielectric cap layer 111, such as a silicon nitride material, a silicon dioxide material and the like, which may cover the electrode material 112, while a sidewall spacer structure 114, for instance comprised of silicon nitride, possibly in combination with an appropriate liner material (not shown), may protect the materials 112 and 113 during the further processing. It should be appreciated that the gate electrode structure 110 may have incorporated therein any sophisticated material systems, such as high-k dielectric materials in the gate insulation layer 113, as will also be described later on in more detail, possibly in combination with metal-containing electrode materials, while in other cases the electrode material 112 is provided in the form of a semiconductor material, such as amorphous or polycrystalline silicon and the like. Furthermore, in some approaches, any other sophisticated material or material systems may be provided in a very later manufacturing stage by replacing at least a portion of the material 112 according to well-established replacement gate approaches. It should further be appreciated that a length of the gate electrode structure 110, i.e., in FIG. 1a, the horizontal extension of the electrode material 112, may be 50 nm and less in sophisticated semiconductor devices.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of any appropriate process strategy. For example, the isolation structure 103C is formed on the basis of sophisticated lithography, etch, deposition and planarization techniques, thereby laterally delineating the active region 103A so as to define the lateral size of the active region 103A in accordance with the design rules. Next, the gate electrode structure 110 may be formed on the basis of sophisticated deposition and patterning strategies, which may also include appropriate process strategies for forming the sidewall spacer structure 114, which may substantially define the lateral offset of cavities 104 to be provided within the active region 103A.
As previously discussed, performance of transistors such as the transistor 120 may be significantly enhanced by creating a specific strain in the channel region 123, which may be accomplished by incorporating a semiconductor alloy having a different natural lattice constant compared to the semiconductor base material of the active region 103A. To this end, the cavities 104 may be formed on the basis of any appropriate etch strategy and subsequently well-established epitaxial growth techniques may be applied in order to grow the semiconductor alloy on the base material of the active region 103A, wherein the mismatch in natural lattice constants between the semiconductor alloy and the base material may thus provide a certain strain component, which may thus be efficiently transferred into the channel region 123, thereby also creating a corresponding “deformation,” which may thus increase charge carrier mobility. The efficiency of the strain-inducing effect may significantly depend on the material composition, for instance on the concentration of germanium in a silicon/germanium mixture, which, however, may be restricted by available deposition recipes, wherein typically a germanium concentration of up to 30 or 35 atomic percent may be practical in view of avoiding undue lattice defects. Other important factors that determine the finally achieved strain in the channel region 123 are the lateral offset of the material from the channel region 123 and the amount of material. These factors may significantly depend on the size and shape of the cavities 104. Upon further reducing dimensions of the transistor 120, superior control of the etch process may be required since any process non-uniformities may over-proportionally affect the final transistor characteristics. Therefore, in sophisticated process sequences, an efficient control mechanism is implemented, in which the result of the etch process for forming the cavities 104 is monitored, for instance, by measuring the degree of material removal and comparing the measured values with a target depth of the cavities 104, which may be in the range of 50-80 nm, depending on the overall process and device requirements.
FIG. 1b schematically illustrates the semiconductor device 100 in an early manufacturing stage in which sophisticated etch processes may also have to be applied in order to form a semiconductor alloy, such as a silicon/germanium alloy, in a corresponding recess. As illustrated, the device 100 comprises the active region 103A and a further active region 103B, which are delineated by the isolation structure 103C, as previously discussed. The active region 103A is to receive a semiconductor alloy so as to modify the electronic characteristics of a channel region of the transistor to be formed in and above the active region 103A, for instance for appropriately adjusting the threshold voltage in combination with a high-k metal gate electrode structure, as is also discussed above. To this end, a recess 105 may be selectively formed in the active region 103A, which may be accomplished by applying sophisticated etch processes, such as wet chemical etch processes on the basis of HCl and the like. Thereafter, the semiconductor alloy may be selectively grown in the recess 105 based on well-established selective epitaxial growth techniques, wherein the active region 103B may be masked by any appropriate dielectric material. It should be appreciated that the resulting threshold voltage may significantly depend on the material composition and the thickness of the semiconductor alloy and thus on the depth of the recess 105. For example, typically, a depth of approximately 10 nm may be required so as to obtain the desired threshold voltage for a given material composition of the silicon/germanium alloy.
FIG. 1c schematically illustrates the device 100 in a further advanced manufacturing stage. As illustrated, a semiconductor alloy 121, such as a silicon/germanium alloy, is incorporated in the active region 103A so as to provide the desired band gap offset, as discussed above. Furthermore, the gate electrode structures 110 for the transistor 120 and a second transistor 120B may be provided in an early manufacturing stage. The gate electrode structures 110 may comprise the gate dielectric material 113 in the form of a sophisticated material system, for instance comprising a high-k dielectric material based on hafnium oxide, zirconium oxide, nitrogen-enriched hafnium oxide and the like. Furthermore, a metal-containing electrode material 115 may be formed on the gate dielectric material 113, wherein, in particular, the material 115 in combination with the semiconductor alloy 121 may determine the resulting threshold voltage of the transistor 120. Therefore, even small variations in layer thickness of the material 121 may result in a significant change of the resulting threshold voltage, which may thus result in a significant variability of transistor characteristics when considering a plurality of the transistors 120. Consequently, in addition to providing a high process uniformity in forming the complex gate electrode structures 110, superior process control for forming the semiconductor alloy 121 is also required, wherein an appropriate provision of the recess 105 (FIG. 1b) is an essential aspect and thus requires a thorough control of the results of the etch process.
It should be appreciated, as indicated in FIG. 1c, that, in this manufacturing stage, for instance after providing any sidewall spacer structure, as previously discussed, the cavities 104 may be provided in the active region 103A, as explained with reference to FIG. 1a. 
FIG. 1d schematically illustrates a measurement strategy in which the quality of sensitive etch processes during any process modules for providing a semiconductor alloy on the basis of a corresponding recess etch process may be monitored. In the case shown in FIG. 1d, it may be assumed that the process for forming the recess 105 is to be monitored, which may be accomplished by using an ellipsometer and a corresponding ultraviolet radiation 106 in order to determine a change in layer thickness caused by the corresponding etch process. To this end, typically, appropriate test areas may be provided, for instance in the scribe line of the semiconductor wafer, i.e., in the vicinity of the actual die region, which may comprise the active regions, which receive the recess 105. The measurement strategy on the basis of an ellipsometer may be efficiently applied to an SOI architecture in which the buried insulating material 102 may provide an appropriate interface with the semiconductor layer 103 in order to optically respond to the probing radiation 106. Consequently, the radiation 106 may be sensitive to changes in layer thickness of several nanometers in order to assess the quality of the etch process for forming the recess 105. Similarly, measurement processes on the basis of elipsometry may also be applied when assessing any etch processes for forming the cavities 104 (FIG. 1a), thereby enabling an efficient control of any process modules for forming semiconductor alloys for sophisticated transistors.
It turns out, however, that elipsometry may not be efficiently used in the context of bulk devices in which the semiconductor layer 103 may directly connect to a crystalline material of the substrate 101 so that an optically active interface, as is provided in SOI configurations by means of the buried insulating material 102, is not available. Therefore, an optically effective thickness of the crystalline material of the layer 103 and a portion of the substrate 101 may be significantly greater than any change of layer thickness caused by the etch processes to be monitored, so that the corresponding measurement sensitivity is insufficient for appropriately evaluating the process sequences of interest.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.